Design and Analysis of Low Power Phase Locked Loop Based Frequency Synthesizer using Cadence Tool

The CMOS PLL based Frequency Synthesizer is a vital role in Receiver front end Sub component. The main objective of this paper is to design a high frequency of oscillation, less phase noise and power efficient PLL. In general, the PLL contains PFD, Loop Filter, VCO and Frequency Divider. The VCO is a critical component in Phase Locked Loop for low power CMOS designs. Here the Source Coupled VCO is proposed, Even though it consumes more power and area.Power dissipation is one of the main important performance parameter now. The Adaptive Voltage level techniques have applied in obtainableeffortmoderate the power dissipation. In this paper provides over all circuit diagram of PLL block diagram. It is designed in CADENCE VIRTUOSO 180nm Technology. Exploiting CADENCE software schematic diagram of overall PLL is drawn and the power, Frequency of oscillation and noise performance are analyzed. KeywordsSource Coupled VCO, PFD, PLL, CADENCE, Frequency Divider and Charge Pump.